To continue Moore's law scaling in future Metal-Oxide-Semiconductor (MOS) technology, a new type of MOS devices, namely Fin Field-Effect Transistors (FinFETs), are become increasingly popular in the manufacturing of integrated circuits. Considering the area cost of integrated circuit design, the FinFETs have increase channel widths over planar transistors since the FinFETs use sidewall regions of fins as parts of the channel regions. The benefit is the saturation currents of the FinFETs accordingly become higher than that of traditional planar devices.
In a typical integrated circuit design process, a circuit schematic of the integrated circuit is generated first, for example, in a schematic editor. Pre-layout simulations are performed to ensure that the schematic of the integrated circuits may meet the design specification. Following the pre-layout simulations, the layout of the integrated circuit is generated, for example, using a layout editor. A design verification is then performed on the layout, wherein the design verification includes Design Rule Check (DRC), Layout Versus Schematic (LVS) verification, Layout Parameter Extraction (LPE), and parasitic Resistance-Capacitance (RC) Extraction (RCX).
After all physical verifications of the integrated circuit design are completed, designers will get layout netlists with parasitic RC network. A post-simulation verification is then performed to determine whether the simulation results meet design specification or not. If the design performance parameters obtained from the post-simulation verification meet the requirement of the design specification, the design can be signed off. Otherwise, the design process loops back to the schematic generation and editing steps, and the steps including the pre-layout simulation, the layout creation, the design verification, and the post-layout simulation are repeated to improve the design. The loop is repeated until eventually the circuit performance parameters meet the requirement of the design specification.